The present application relates generally to electronic devices, and more specifically to strain-engineered electronic devices and their methods of production.
In the electronics industry, packaging density continuously increases in order to accommodate more electronic devices into a package. In this regard, three-dimensional (3D) stacking technology of wafers and/or chips contributes to the device integration process. Typically, a semiconductor wafer (a semiconductor device/substrate) or chip (a semiconductor device) includes several layers of integrated circuitry (e.g., processors, programmable devices, memory devices, etc.) built on a silicon substrate. A top layer of the wafer may be connected to a bottom layer of the wafer through silicon interconnects or vias. Typical vias include conductive material formed in cavities in the semiconductor substrate that electrically connect conductive contacts disposed in different areas of a device. In order to form a 3D wafer stack, two or more wafers are placed on top of one other and bonded together.
The formation of through-substrate vias (TSVs) typically includes etching or drilling into the substrate to form openings, and then filling the openings with a conductive material. Excess conductive material may be removed, e.g., via planarization using chemical mechanical polishing. The remaining portions of the conductive material in the substrate form the TSVs.
The formation of the through-substrate via creates an adjacent stress field in the substrate. It has been observed that the induced stress and its attendant strain field may have an adverse effect on the performance of devices located proximate to the TSVs. Thus, it would be advantageous to form strain engineered TSVs whose negative impact on neighboring devices is minimized